algrobman

I've added all RV32ZB* and RV32B to the list of supported ISA, but no bitmanip instructions were generated ...

AxID , RID and BID are used to relate requests and responses on AXI bus to allow out of order responses, speeding up bus operation. If you need bus with...

the same issue is for vfmv.f.s - always selects ft0 FPR ...

I fixed this in riscvdv/src/isa/riscv_vector_instr.sv: virtual function void set_rand_mode(); string name = instr_name.name(); has_rs1 = 1; has_rs2 = 0; **has_rd = 1;** has_fs1 = 0; has_fs2 = 0; has_fs3 =...

BTW, why do the handlers save/restore all GPRs while only a few are used /changed in the handlers?

yes, it is. BTW, does somebody maintain this repo? Why isn't this fixed in master/latest?

@dpetrisko , thanks for pointing the fix

there are a few more cases where the code could be optimized for speed and maybe code size, assuming the buffers are DW aligned. the block structure can be represented...

Tim, > So that a debugger can discover XLEN by attempting a 64-bit access and seeing whether it succeeds or fails. Do we still really need to implement specific to...

> > Also why is DCSR defined as 32 bit CSR even for 64 bit machine? > Probably to keep the specification simpler. How does it make it simpler? it...