algrobman

verilog.dump is your VCD waves

this is verilator bug - ask the tool developer to fix this. A verilog simulator supposed to support verilog standard which allows functions definitions without qualifiers. Verilator should issue Note...

there would be better way to use proprietary SRAMs RTL memories library modules can be replaced with custom onces, instantiating memory vendors verilogs ...

does this really work? see https://github.com/chipsalliance/Cores-VeeR-EL2/issues/163

Are you sure this change is compatible with JTAG standard and RISCV debug spec?

1) you can't use simple synchronizers to pass a bus to another clocking domain. You'll get bit divergence. 2) there is no need in the synchronizers for buses passing between...

tdoEnable output is meant to tristate real SOC TDO pin. Since debug subsystem is not alone is a SOC, but connected to the SOC JTAG someway, there is no sense...

BTW, what is this picolibs stuff for?

cd el2/Cores-VeeR-EL2/third_party/picolibc && meson el2/Cores-VeeR-EL2/third_party/picolibc/build \ -Dmultilib=true \ -Dmultilib-list=rv32imac/ilp32 \ -Dpicocrt=false \ -Datomic-ungetc=false \ -Dthread-local-storage=false \ -Dio-long-long=true \ -Dformat-default=integer \ -Dincludedir=picolibc/riscv64-unknown-elf/include \ -Dlibdir=picolibc/riscv64-unknown-elf/lib \ -Dprefix=el2/Cores-VeeR-EL2/third_party/picolibc/install \ -Dspecsdir=el2/Cores-VeeR-EL2/third_party/picolibc/install \ --cross-file el2/Cores-VeeR-EL2/third_party/picolibc/build/cross.txt...

Don't you think that not all users need this picolibc and it shouldn't be built in main Makefile if I want to run just hello_world?