algrobman

> I still suspect a time zero race between the initial and the assignment, with X's. Put a display in the always loop, and see how on Xcelium to get...

here $displays for Xcellium: ``` before a=01 after a=02 a=02, dec=02 enc=6 T=10 before a=02 after a=04 a=04, dec=04 enc=5 T=20 before a=04 .. ``` Here for verilator: VerilatorTB: Start...

statements with T= are $display at negadge clk ..

looks like all this because of my C++ code: ``` int main(int argc, char** argv) { std::cout open ("sim.vcd"); #endif // Simulate while(!Verilated::gotFinish()){ #if VM_TRACE tfp->dump (main_time); #endif main_time +=...

one more problem: Cadence/Synopsys tools could not read VCD produced by Verilator. ``` $version Generated by VerilatedVcd $end $timescale 1ps $end $scope module $end $scope module $unit $end $var wire...

> Perhaps you're not creating the Verilated model with a name and that gets passed through? Not sure I understand your question. My run script/TB/RTL content did not change. I...

Wilson, thanks again. Now I got to our initial problem - xrun/verilator simulation difference with verilog checking for Xs: here is the problematic module: ``` module lzd (a,enc,dec); parameter a_width...

You are right about '===' , but we got this code from a third party and warn them about it. Regardless, X,Z usage warning could save a lot of debug...

Are you going to fix all these issues?

I meant to add at least warnings for usage of X/Zs and fixing "empty/unnamed" $scope module statements in VCD any soon.