Tim Hutt
Tim Hutt
Add static type hints, and switch to literals for some dicts to improve type inference (and it's nicer code anyway). This makes the code easier to understand and navigate, and...
Hi, I was wondering if you would be open to PRs to improve the general software engineering quality of this repo. This is the sort of thing I'm thinking of...
The table [Currently allocated RISC-V unprivileged CSR addresses](https://riscv-specs.timhutt.co.uk/spec/20240411/priv-isa-asciidoc.html#ucsrnames) is missing all of the vector registers: * `vstart` * `vxsat` * `vxrm` * `vcsr` * `vl` * `vtype` * `vlenb`
There are still some comments like this: > The definition of the STCE field will be furnished by the forthcoming Sstc extension. Its allocation within menvcfg may change prior to...
`pmpaddr` uniquely contains writable bits that "read as" some value, but have an underlying value that can be different. The behaviour when you modify *different* bits in the CSR using...
This is the suggestion from https://github.com/riscv/riscv-CMOs/issues/57#issue-1573765692 which was never applied. The behaviour can be technically inferred from this paragraph - as noted in one of the comments on that issue:...
When setting PC to a vectored address on trap or xRET, the spec says: > If the fetch is successful, the hart clears the low bit of the handler address...
> For backwards compatibility in implementations supporting both CLINT and CLIC modes, when switching to CLINT mode the new CLIC xcause.xpil state field is zeroed. > For backwards compatibility in...
I think the specification for `xscratchcsw[l]` could be significantly simplified and tightened up to avoid implementation defined behaviour by changing it to be something like this: > `xscratchcsw` and `xscratchcswl`...
Without looking at the pseudocode, the definition of `xscratchcswl` is > This new CSR operates similarly to xscratchcsw except that the swap condition is true when the interrupter and interruptee...