Tim Hutt
Tim Hutt
This code: ``` function legalize_mip(o : Minterrupts, v : xlenbits) -> Minterrupts = { /* The only writable bits are the S-mode bits, and with the 'N' * extension, the...
### Steps to Reproduce ``` curl -sSf https://rye.astral.sh/get | bash # Pick `uv`, `Run a Python installed and managed by Rye', `default cython 3.12`, `yes add to .profile` source .profile...
It's not a great name because it really gates access to all CHERI features - not just registers; you can't use instructions either. Difficult to think of a really good...
Hey, just an idea for a rule: if you indent `ifeq` with tabs then apparently older Make versions will just ignore it (it is considered part of the rule) but...
There are some vector functions that return bit masks as a vector of bools, rather than a `bits()`. This makes the code unnecessarily complex. See https://github.com/riscv/sail-riscv/pull/552#discussion_r1768236101
> One thing I noticed is the read_vmask_carry function doesn't seem to be doing anything, as it looks like it is only called with vm=0b0 where it is then the...
VLEN and ELEN are implementation defined configuration parameters for the vector extension. Currently the implementation stores them in registers: ``` register elen : bits(1) val get_elen_pow : unit -> {5,...
The model contains ``` register vlenb : xlenbits ``` However this register contains no state and simply returns a hardcoded value `VLEN/8` which is fixed at implementation time (it can't...
The type declarations for those division operators are missing `>0` and `>=0` constraints. See https://github.com/riscv/sail-riscv/pull/552/files#r1768223964
When FLEN != XLEN there are some compilation issues in the `fmv` D instructions. Current code is: ``` function clause execute (F_UN_TYPE_D(rs1, rd, FMV_X_D)) = { assert(sizeof(xlen) >= 64); let...