Tim Hutt
Tim Hutt
The instructions apparently don't check that e.g. for LMUL=4 you don't use `vs1=x3` - you have to use a multiple of LMUL for the register index. We need to add...
We should support testing against [riscv-arch-test](https://github.com/riscv-non-isa/riscv-arch-test) (AKA ACTs), and run these tests in CI. This was previously discounted because they test against Sail, but that only happens after PRs have...
See [this idea](https://github.com/riscv/sail-riscv/issues/1002#issuecomment-2948711981). We can loop through all opcodes, disassemble them with Sail then reassemble them with GAS and verify we get the same result. I have code for this...
AIA ([specification](file:///home/codasip.com/timothy.hutt/Downloads/riscv-interrupts-20250312.pdf)) adds a number of CSRs and widens some existing ones. `miselect` and `mireg` are shared with the indirect CSR access extension Smcsrind, and provide a way to access...
Currently `write_CSR()` returns the new value of written CSRs, purely for logging. This is pretty tedious though. Since none of the CSRs actually have read side effects, instead we can...
This function is used to provide random data to the `seed` CSR: ``` // Provides entropy for the scalar cryptography extension. uint64_t rv_16_random_bits(void) { // This function can be changed...
This code is missing `vcsr[vxsat] = 0b1;` ``` VV_VSSUBU => { if unsigned(vs2_val[i]) < unsigned(vs1_val[i]) then zeros() ``` That code looks a bit suss to be honest - why is...
These instructions move whole vector registers and never operate at an element level. It looks like it doesn't handle this either: > The usual property that no elements are written...
After #494 is done we should move the RVFI protocol implementation out of Sail and into C.
In support of #1008 it's helpful to have `encdec` not decode reserved instructions that don't have legal assembly. One case is when you try to write to `v0` with a...