Tim Hutt
Tim Hutt
Rework the text to be much more explicit about the behaviour when rs1 is not aligned to the cache block size. I also moved & slightly reworded the note about...
This part of the spec was written before the RVWMO section which introduced the "memory operation" nomenclature. This updates the section to talk about memory operations instead of memory accesses....
With the `-r` / `--randomize` flag, riscv-ctg uses `python-constraint`'s `MinConflictsSolver`. This is not reproducible. It seems like this was noticed at least: > A obvious down-side of using random solvers...
It's pretty confusing that the directory where the RISC-V CGF files are stored is called `sample_cgfs`. When I first saw it I thought "ah those are some samples, but where...
PyYAML has really really bad performance when adding comments, so I changed it to only add them for the first 100 entries. I also removed the `l+i` offset which doesn't...
Can we remove the OCaml emulator? I think this would have significant benefits: * Less confusing for new users - they no longer need to choose between two very similar...
I think the `haveExtension()` functions are a bit confusingly named. It's unclear whether they mean that the CPU *supports* the extension, or if it is currently *enabled* (which are not...
Store conditional speculative failures currently can happen as soon as a SC is executed: ``` function clause execute (STORECON(aq, rl, rs2, rs1, width, rd)) = { if speculate_conditional () ==...
This is defined already by Sail now.
The flags and result for a softfloat operation are currently pushed to the Sail code from C like this: // C zfloat_result = res.v; zfloat_fflags = (mach_bits)softfloat_exceptionFlags // Sail register...