Specify the interaction between CSRRS/C and "reads as" bits

[Timmmm]

pmpaddr uniquely contains writable bits that "read as" some value, but have an underlying value that can be different. The behaviour when you modify different bits in the CSR using csrr{sc}[i] was not clear.

This is the behaviour that the Sail model, SPIKE and the open-source Rocket core all implement.

[pdonahue-ventana]

IIRC, this also affects mepc[1] if misa.C is writable.

[Timmmm]

Ah yes you're right:

If an implementation allows IALIGN to be either 16 or 32 (by changing CSR misa, for example), then, whenever IALIGN=32, bit mepc[1] is masked on reads so that it appears to be 0. This masking occurs also for the implicit read by the MRET instruction. Though masked, mepc[1] remains writable when IALIGN=32.

For completeness, here's the discussion on the mailing list. The proposal there (which I don't really like) is to make it implementation defined.