Clarify CBO for unaligned rs1

[Timmmm]

Rework the text to be much more explicit about the behaviour when rs1 is not aligned to the cache block size.

I also moved & slightly reworded the note about the assembly syntax since it's not relevant to the instruction semantics.

Fixes #1263

[Timmmm]

@ved-rivos @dkruckemyer-ventana any objection to merging this? I think the points Ved raised above are pre-existing issues (unless I've misunderstood) and therefore can be addressed in another PR.