Tim Hutt
Tim Hutt
Also minor formatting cleanups and simplifications, and I fixed a typo `bi`->`bin` typo. Fixes #8
This has caused some confusion so is worth being very clear about.
The old wording was slightly confusing and ambiguous - why does it mention leaving the other metadata unchanged, when this instruction only ever changes the tag? This is hopefully a...
On current `master`, the following command takes a very long time: ``` ❯ time cargo run --release --example syscalls -- ls Finished release [optimized] target(s) in 0.01s Running `target/release/examples/syscalls ls`...
### Feature Request I have a project that works fine with intellisense except for one enormous file which is 200k lines long (it's generated). If I open that file than...
Test case: ``` // main.sv module top(); module_with_a_very_long_name_this_is_autogenerated_so_its_not_unreasonable_and_it_really_has_to_be_quite_long_to_trigger_this_bug u_thing(); always begin assert(u_thing.foo == 1'b1); end endmodule; ``` ``` // module_with_a_very_long_name_this_is_autogenerated_so_its_not_unreasonable_and_it_really_has_to_be_quite_long_to_trigger_this_bug.sv module module_with_a_very_long_name_this_is_autogenerated_so_its_not_unreasonable_and_it_really_has_to_be_quite_long_to_trigger_this_bug(); logic foo; endmodule; ``` Error: ``` ❯ verilator...
Hi, I am very new to OCaml but I've been working on [the Sail compiler](https://github.com/rems-project/sail) which is written in OCaml using VSCode and ocaml-lsp. Generally the LSP works very well,...
This allows it to be used repeatably.
Rework the text to be much more explicit about the behaviour when rs1 is not aligned to the cache block size. I also moved & slightly reworded the note about...
This part of the spec was written before the RVWMO section which introduced the "memory operation" nomenclature. This updates the section to talk about memory operations instead of memory accesses....