OpenLane
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The-OpenROAD-Project
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
### Prompt Current MPW-6 Openlane has common config to decide on number of core ring and power strip. Issue: In MPW shuttle user project need have core-ring for all the...
@jjcherry56 points out that we should have the option of calling `remove_buffers` before we call `repair_design`, to undo any buffer addition that yosys/abc does. To complicate matters, Openlane currently has...
### Description Issues with loading lef/def files in magic layout generated using openlane, after caravel integration with user_project_wrapper. ### Environment ``` Kernel: Linux v3.10.0-1160.24.1.el7.x86_64 Distribution: centos 7 Python: v3.9.7 (OK)...
### Description Hello everyone, I tried to run user_project_wrapper with my design inside. There is a mismatch in LVS stage, which outputs the log message below. ``` LVS reports: net...
### Description Inputs should by default have antenna diodes to protect them during fabrication. ### Environment ``` Kernel: Linux v5.13.0-40-generic Distribution: ubuntu 20.04 Python: v3.8.10 (OK) Container Engine: docker v20.10.7...
### Prompt The `FP_PDN_AUTO_ADJUST` flag, as implemented [here](https://github.com/The-OpenROAD-Project/OpenLane/blob/master/scripts/tcl_commands/floorplan.tcl#L67) currently sets the pitch and offset of the power grid by dividing the core width and height by the hard-coded values 4...
### Description Imagine we have a macro1, which has inout and it connects it's output to one. Then there is macro2 which is made using OpenLane which has inout and...
### Description Hello everyone, I am trying to implement SRAM macros inside caravel user area. Everything works fine until DRC step. In the DRC step, I get this error message....
In https://github.com/efabless/caravel/issues/41 @rtimothyedwards mentions: > It is also unclear to me why openlane uses "clkbuf" buffers for input buffering. There is no particular need for an oversized balanced > buffer...
Having an open source toolchain for synthesizing integrated circuits can be really useful for research projects. However, some industries enforce the use of vhdl, which is not highly supported by...
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OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.