OpenLane
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The-OpenROAD-Project
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
### Description My SOC project has Multiple Hardmarco and all these hardmacro had power hook up in met-3/met-4. Recently i have added a new macro which had power hook-up of...
### Description Hi, I am trying to do a manual macro placement with OpenLane. When the macros are relatively large, the manual macro placement was implemented well. However, with the...
### Prompt Current netlists in OpenLane, due to historical limitations with OpenROAD, do not keep the hierarchical names for nets, replacing them with numbers. ### Proposal Let's not.
### Prompt People use OpenLane for small designs. However many small designs do not fit PDN grid properly and have some weird quirks and issues. ### Proposal Have a `MIN_DIE_AREA`...
### Prompt Currently OpenLane has no support for multi voltage theshold libraries. Support for this feature would enable more flexibility and overall better PPA. ### Proposal Add support for Multi-VT...
WIP --- \+ Create OpenROAD script `common` folder, isolating common code into a folder instead of the preceding chaos \+ New functions `merge_lib`, `set_verbose`, `set_sdc` created \+ Add `CURRENT_POWERED_NETLIST` to...
WIP, cannot be merged until `open_pdks` and `volare` are updated. --- + Add gf180mcuC configs for {APU, PPU, SPM} ~ Clean up some leftover variables ~ STD_CELL_LIBRARY now an optional...
### Description I have successfully generated GDSII file with open lane for picorv32 with configuration using docker container. However when I try to get GDSII for Rocket chip with Tiny...
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OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.