PeakRDL-regblock
PeakRDL-regblock copied to clipboard
SystemRDL
Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
Hi, does PeakRDL-regblock generated register map support clock gating ? I see that each generated register is clock enabled, so inferred clock gating will kick in for individual registers /...
Hi, when trying to synthesize the generated register map with Design compiler, I get warnings due to assertions that check the generated block behavior: ``` Line 1289: Warning: /tmp/dummy_block.sv:83: The...
I am trying to run peakRDL regblok on a block that we are designing. Currently, we are using ORDT, but since the ORDT is not mainteined anymore, we might be...
I propose a new feature: the ability to enable response with an error if the address was decoded incorrectly. Sometimes it is necessary to describe a register map so that...
Is there any reason why this restriction exists? https://github.com/SystemRDL/PeakRDL-regblock/blob/a076609dad8f876f556144786a2af3ae4d46a7fd/src/peakrdl_regblock/validate_design.py#L164-L197 Would it be possible to simply subtract the component absolute address? https://github.com/SystemRDL/PeakRDL-regblock/blob/a076609dad8f876f556144786a2af3ae4d46a7fd/src/peakrdl_regblock/field_logic/templates/external_block.sv#L25 ```verilog assign {{prefix}}.addr = decoded_addr - 'h{{raw_absolute_address}}; ```
https://peakrdl-regblock.readthedocs.io/en/latest/cpuif/internal_protocol.html#read-response > Read data. The width of this is bus is determined by the size of the largest register in the design. But the code looks at largest minimum access...
If an asynchronous reset is employed, the value of field_logic.get_next_q_identifier gets updated when the reset signal changes, even though the clock hasn't changed. This causes an unwanted update in the...
The `hwset` property does not work as I expect on multi-bit fields. Instead of a `hwset` input port matching the width of the field, it is always a single bit,...
This PR adds new classes to handle sticky/stickybit fields with WE/WEL property set. It also removes some classes that were design for edge sensitive nonsitcky fields. As far as I...
Hi Alex, I managed to hit an assert and looking at the SystemRDL 2.0 Spec it is not clear to me why that is happening. I found empirically that I...
