Unaligned external addressable components

[maltaisn]

Is there any reason why this restriction exists?

https://github.com/SystemRDL/PeakRDL-regblock/blob/a076609dad8f876f556144786a2af3ae4d46a7fd/src/peakrdl_regblock/validate_design.py#L164-L197

Would it be possible to simply subtract the component absolute address?

https://github.com/SystemRDL/PeakRDL-regblock/blob/a076609dad8f876f556144786a2af3ae4d46a7fd/src/peakrdl_regblock/field_logic/templates/external_block.sv#L25

assign {{prefix}}.addr = decoded_addr - 'h{{raw_absolute_address}};