VexRiscv
VexRiscv copied to clipboard
SpinalHDL
A FPGA friendly 32 bit RISC-V CPU implementation
I modified CustomCsrDemoPlugin and trying to read the value from this CSR register to a variable (line no.13 in the below code snippet) which I am observing in an Oscilloscope....
Hi, I generated the Briey SoC with FPU Plugin with the following configuration: ``` new FpuPlugin( externalFpu = false, p = new FpuParameter( withDouble = false ) ), ``` For...
At the VexRiscv commit used by pythondata-cpu-vexriscv to build the verilogs, there is a clash in the use of CSR 0xBC0, used both by CfuPlugin for its state/index/enable register, and...
Hi, Can someone provide more details on the synthesis data shown? i.e. did the synthesis run include FP register file, instruction decode/issue logic? Much appreciated! > Fpu 32 bits ->...
When I ran this command, sbt "runMain vexriscv.demo.GenFull", the following error occurred. Please help. Thanks! mji@XPS-8930-5:~/VexRiscv/verilator$ sbt "runMain vexriscv.demo.GenFull" [info] welcome to sbt 1.6.2 (Private Build Java 11.0.15) [info] loading...
based on Briey VexRiscv, I generated a variant with 32-bit single precision float extension and on-chip debug and implemented it on an Altera board. Preloaded floating point code works. Debugging...
CHERI adds some extra hardware functionality which software can take advantage of to do advanced memory protection and such. https://www.cl.cam.ac.uk/research/security/ctsrd/cheri/ https://www.cl.cam.ac.uk/research/security/ctsrd/cheri/cheri-risc-v.html https://www.cl.cam.ac.uk/techreports/UCAM-CL-TR-951.pdf
This is not a bug, I would just like to discuss some of my findings. I choose VexRiscv, since it seems to be the the most prominent FPGA implementation of...
Hi, I want to generate VexRiscv and Briey with Double FPU plugin. I'm a newby in SpinalHDL system. How can I do this? Thanks.
