Adding FPU

[ghost]

Hi,

I want to generate VexRiscv and Briey with Double FPU plugin. I'm a newby in SpinalHDL system. How can I do this? Thanks.

[Dolu1990]

Hi,

So, as a first step i would say the best is with the Float FPU, (because the double FPU require 64 bits bus, which would require a few more modification in Briey).

So for Float FPU, you need to add the FpuPlugin to the VexRiscv config, and that's it.

So, for instance after https://github.com/SpinalHDL/VexRiscv/blob/master/src/main/scala/vexriscv/demo/Briey.scala#L133

new FpuPlugin(
  externalFpu = false,
  p = FpuParameter(
    withDouble = false
  )
)

[ashuthosh-mr]

@Dolu1990

Hi,

I compiled the C code which has floats using -mabi=ilp32 -march=rv32imaf, but get error:

libc.a(lib_a-memcmp.o): ABI is incompatible with that of the selected emulation: target emulation elf64-littleriscv' does not match elf32-littleriscv and many more errors with ABI is not compatible . However, when I use -mabi=ilp32d -march=rv32imafdc, it compiles but do not simulate on a GenFull vexriscv with FPU as it gets stucks in the simulation.

My thoughts: I think double is 64bit but it is not configured rightly in the FPU plugin of the vexriscv leading to stuck in simulation. How can I succesfully compile the C code involving floats and double. (Also, I do not understand why Floats get emulated when march=rv32ima but they fail to emulate double when march=rv32imaf is used although there is no support for double for instance.)

Thank you so much.

[ashuthosh-mr]

Also, on the hardware side of the story,

  externalFpu = false,
  p = FpuParameter(
    withDouble = true
  )
)

I made withDouble = true. I have changed the memdatawidth(ibus), cpudatawidth (dbus) and memdatawidth(dbus) to 64. What other changes might be needed in the vexriscv scala to generate the GenFull with rv32imafdc?

[Dolu1990]

I would say, start first with 32 bits floating point only, to not add the additional 64 bits memdatawidth bus complication.

However, when I use -mabi=ilp32d -march=rv32imafdc, it compiles but do not simulate on a GenFull vexriscv with FPU as it gets stucks in the simulation.

When you run the simulation with 64 bits mem data width, you also need to specify a few define to the make command, have you done so ? else The simulation will assume 32 bits data bus