VexRiscv Ping me if you are waiting a feedback/answer to one of your issues :)

Ping me if you are waiting a feedback/answer to one of your issues :)

Open Dolu1990 opened this issue 4 years ago • 18 comments

Jan 08 '20 20:01 Dolu1990

vexRiscV support up to 5 pipeline stage. how to configure to instance each stage? for example, which plugin to instance IF, which to instance DEC and so on... If I want to instance a RV32IMAC core, 2 pipeline (IF-DEC/DEC-EXE), or 3 pipeline (IF/DEC/EXE), how to write my configuration? I known there are many demos , but no detials about pipeline stages.

Thanks for your work.

Oct 28 '20 08:10 curliph

So basicaly the memory/writeback stages aren't added by plugin, but by the VexRiscvConfig : https://github.com/SpinalHDL/VexRiscv/blob/dev/src/main/scala/vexriscv/demo/GenTwoThreeStage.scala#L12 see withMemoryStage, withWriteBackStage

Then the fetch stages are added by the IBusSimplePlugin/IBusCachedPlugin,for instance here it specify no fetch stage : https://github.com/SpinalHDL/VexRiscv/blob/dev/src/main/scala/vexriscv/demo/GenTwoThreeStage.scala#L23

The main limitation is that the decode stage can't be merged in the execute stage currently, but else all can be merged

Oct 28 '20 09:10 Dolu1990

Thanks a lot, Dolu~

Oct 28 '20 09:10 curliph

help https://github.com/SpinalHDL/VexRiscv/issues/209