VexRiscv
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openocd debugging with FPU
based on Briey VexRiscv, I generated a variant with 32-bit single precision float extension and on-chip debug and implemented it on an Altera board. Preloaded floating point code works. Debugging with the current openocd_riscv also works, but only as long as the code to debug does not use the float unit. When attempting to debug code with floating point instructions, a connection from riscv64-unknown-elf-gdb to openocd_riscv failed with error message
bfd requires flen 4, but target has flen 0
The debugger doesn't seem to recognize the floating point extension. How does the debugger actually recognize the CPU configuration? How can this be parameterized?
Hi,
Yes it is "expected". I just documented now why it happen : https://github.com/SpinalHDL/VexRiscv/commit/9772e6775dde1f2b62f1ceb3525034d5e6782142
So you need to use the GDB from https://static.dev.sifive.com/dev-tools/riscv64-unknown-elf-gcc-20171231-x86_64-linux-centos6.tar.gz and compile the code in -O0 :)