FPU Synthesis Detail

[gyh1997127]

Hi,

Can someone provide more details on the synthesis data shown? i.e. did the synthesis run include FP register file, instruction decode/issue logic? Much appreciated!

Fpu 32 bits -> Artix 7 relaxed -> 135 Mhz 1786 LUT 1778 FF Artix 7 FMax -> 205 Mhz 2101 LUT 1778 FF Fpu 64/32 bits -> Artix 7 relaxed -> 101 Mhz 3336 LUT 3033 FF Artix 7 FMax -> 165 Mhz 3728 LUT 3175 FF

[Dolu1990]

Hi ^^ It does include the FP register file and all the floating point operations + convertions, but not the instruction decoding / issue (if i remember well).

In other words, everything on the FPU side of https://github.com/SpinalHDL/VexRiscv/blob/master/assets/fpuDesign.png?raw=true

[Dolu1990]

Also, note that i recently ported the FPU to NaxRiscv, with full compliance this time, and a few design changes.

[Dolu1990]

naxriscv => https://github.com/SpinalHDL/NaxRiscv/blob/main/src/main/scala/naxriscv/execute/fpu/FpuCore.scala

[gyh1997127]

Thank you!