Fabien Marteau

Corescore on spartan6

4

I'm trying to add my board[ opos6ul_sp in the corescore project.](https://github.com/Martoni/corescore/commit/29af1313cc7e7f0842cfce885bacbe6f50cd98b0) but I'm stuck with a $clog2() problem. ``` ERROR:HDLCompiler:815 - "/…/workspace/build/corescore_0/src/serving_1.0.2/serving/serving.v" Line 42: System function call clog2 is not...

I managed to synthesize corescore for colorlight_5a75b. Seems to works but if I open terminal on uart I have an end of line problem : ```shell $ screen /dev/ttyUSB0 57600...

Is there a reason why `Analog()` direction port type is still in [experimental module ](https://www.chisel-lang.org/api/latest/chisel3/experimental/Analog.html)? It has been used for a long time in several project. It's very useful for...

feature request: PSL support for formal verification.

1

I [tried some Formal verification](https://github.com/Martoni/HdmiCore/blob/main/src/test/scala/TmdsEncoder.scala#L50) with chisel-tester2 [thanks to](https://github.com/Martoni/HdmiCore/pull/2) @ekiwi help. It works but I wonder if there is a plan to support [PSL langage](https://en.wikipedia.org/wiki/Property_Specification_Language) like [it's done with GHDL](https://github.com/tmeissner/psl_with_ghdl)....

library for testing standard components like wishbone, uart, ...

4

Is there some examples or standard libraries for testing components like wishbone, uart, spi, ... with chisel-testers2 ?

Roadmap for a release

1

Is there a Roadmap for a release of this project ? I'm using it intensively for Verilog conversion in conjunction with verilator to boost simulation performance. I'm also using it...

Cocotb directives in Verilog backend

2

I'm using [cocotb](https://github.com/potentialventures/cocotb) to write my testbench. Because it's in python and it's easier than writing verilog testbench. But to simulate verilog generated by chisel I have to modify the...

risingedge function is given as example in Chisel tutorial : ``` scala def risingedge(x: Bool) = x && !Reg(next = x) ``` It's a really usefull function I redefine in...

I have a problem with compiling a module that use two domain clock. I'm re-writting the AsyncFifo to include the ability to flush it. Here the code :: ``` Scala...

little spelling correction