Fabien Marteau

Generate verilog formal code only in systemVerilog output

12

As comment say : ``` ------------------------------------------------------------------------------ Warning: 5 verification statements (assert, assume or cover) were removed when compiling to Verilog because the basic Verilog standard does not support them. If...

On my Linux debian Jessie computer i could'nt run or assembly the game without these modification. regards.

Just avoiding warnings when compile with clang-3.5 or clang-3.8.

Why using clang-3.6 ? In my debian I have clang-3.5 and 3.8. Do you think that we can use clang-3.8 instead of 3.6 ? I just tested, it's compile well...

HD1080p and HD720p valided

I see that last release of chisel-template is on 2018. Is it the latest ? It's not following Chisel release ? thx

[a copy from chisel repository [issue](https://github.com/freechipsproject/chisel3/issues/1105)] **Type of issue**: documentation **Impact**: no functional change **Development Phase**: request **Other information** Is it possible to add Vec initialization ? For example, here...

Write VCD file

1

Is it possible to write in vcd file ? Could be useful to annotate vcd traces.

Ville étrangère & voies vertes allemandes

5

Merci pour cet outils génial. J'aime bien le concept de s'écarter des enquêtes d'opinions et de se baser sur la «réalité» pour établir le score. J'ai pu obtenir facilement le...

How to syntesize and place & route for CLEAR ?

1

Hello, Is there a tutorial to explain step by step how to synthesize a design and place & route for CLEAR eFPGA ? And also, is there static timing analyser...