Fabien Marteau comments

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                                            Fabien Marteau

Corescore on spartan6

I haven't tested it since. The problem is that ISE doesn't recognize $clog2() function used in `serving.v`. As ISE is freezed in old version and will not be updated it...

Gowin GW2A-55 support

Hi @tinylabs, your error seems to be same with other gowin as reported in this [issue](https://github.com/trabucayre/openFPGALoader/issues/14).

library for testing standard components like wishbone, uart, ...

Writing testbench is the most time and resource consuming part of the development process. If we could get some basic bricks to ease and speed up development it would make...

Cocotb directives in Verilog backend

@aswaterman Yes I do that, but with this solution I need to maintain one more source file. [I wrote a little quick&dirty python script ](https://github.com/Martoni/cocotbify)to add these lines just after...

Generate verilog formal code only in systemVerilog output

I' wondering if it's possible to add this option in `src/main/scala/chisel3/formal/formal/Driver.scala` or if it should be put somewhere else ?

Generate verilog formal code only in systemVerilog output

> @Martoni is it the case that if these two modules had a Verilog timescale set then that would fix the issue for you? If so that's probably the easiest...

Generate verilog formal code only in systemVerilog output

> Does that fix your use case? I will try it.

Generate verilog formal code only in systemVerilog output

It's work with verilator. But it would really be better if ResetCounter and TestCase are not generated. But it's work as it.

Generate verilog formal code only in systemVerilog output

This lines should be removed from pure verilog sources I think : ```Verilog wire ResetCounter_clock; // @[Formal.scala 14:36] wire ResetCounter_reset; // @[Formal.scala 14:36] wire [31:0] ResetCounter_numResets; // @[Formal.scala 14:36] wire...

Generate verilog formal code only in systemVerilog output

I made a [quick&dirty](https://github.com/Martoni/chisverilogutils/tree/master/chiselformalcleaner) script to suppress it.