Michael Jørgensen

One more comment. If the problem indeed is inside the HyperRAM controller, there is a timing parameter that can be tweaked. The value for `IDELAY_VALUE` in line 62 in `hyperram_rx.vhd`....

I think you're on to something. The good news (for me!) is that the HyperRAM controller seems to work as intended: The Avalon protocol is a bit "fragile" in the...

Since you mentioned timing violations, I ran a build (from tag v0.00012) without debug and indeed found many timing violations. I would strongly urge you to fix these violations before...

It might be that items 1 and 2 in my above comment is enough to allow us to proceed with the debugging. Because I just had a look at your...

I see you've fixed the timing violations. Well done! From your observations, I thought the bug could perhaps be a problem with reset. Anyway, I tried building using the branch...

Oh, and a quick comment on your latest traces (03a-reset-black-screen): I notice in clock cycle 8118 that `hr_address` changes from 0x11f00 to 0x11f40. This suggest to me that a new...

Ok, I got the core working. My problem was I was viewing the VGA output and therefore did not see the Welcome screen, and it didn't occur to me to...