Michael Jørgensen

@sy2002 : Maybe we should inform Volker about this change? The way I see it, with these new changes, an ISR can use all registers R0-R12, and not just R0-R7....

Volker replied by mail and questioned our design. I think perhaps it is time to sit down and re-evaluate. The reason is that with the current compiler interrupt handling does...

Re 2) Yes, that is correct. I still think this is a very special use case, and not something that a casual user writing an ISR in C would need....

I tried with speed grade -1 using Vivado to build for the Nexys4DDR board, and it closes timing without problem. I've therefore updated to grade -1, and closing this issue.

The test program `test_isr.c` runs fine on the emulator, but when the user presses a key, the emulator ends with the following message: ``` [1, 0] timer could not be...

These four commands will compile the C program ``` $ cd c $ source setenv.source $ cd test_programs/ $ qvc test_isr.c ```

I just ran the `strace` command with the emulator and got the following output: ``` read(0, "q", 1024) = 1 openat(AT_FDCWD, "/etc/ld.so.cache", O_RDONLY|O_CLOEXEC) = 3 fstat(3, {st_mode=S_IFREG|0644, st_size=134800, ...}) =...

Once more, this time with `DEBUG` enabled: ``` read(0, "q", 1024) = 1 write(1, "timer: write access at address 0"..., 37timer: write access at address 0000. ) = 37 futex(0x7f1aa06a64c0,...

I like the idea of pause/resume. But that still requires two instructions in the beginning of a Monitor function: ``` MOVE IC$CSR, R0 OR 0x0002, @R0 ; Set bit 1...

@bernd-ulmann That's exactly what I'm looking for! We can discuss this tonight, but it seems to me this is the best solution. However, there is one thing: We will want...