Jonathan Balkind

That's entirely dependent on the environment. If you have an UltraScale+ VU9P part (like the vcu118 or Amazon F1) you should be able to reach 125MHz. On Kintex 7 (Digilent...

Did you also regenerate the IPs for the new frequency? `clk_mmcm` is the one generating the clock at the new frequency. `block.list` only helps generate the bootrom and so on.

Should be, yeah

Try switching to openpiton-dev. I think we had the F1 submodule set to use SSH instead of HTTPS. That should be fixed in openpiton-dev. Then if you run the `git...

Looking at the code, this version assumes that it has some kind of test harness that doesn't exist in our environment. You'd have to modify the compilation environment to instead...

I could get it to build by copying `$PITON_ROOT/piton/verif/diag/assembly/include/riscv/ariane/*` into the `riscv-coremark/riscv64-baremetal/` directory and then modifying the gcc build command to add `-fno-builtin-printf`. However, I get bad trap when it...

Looks like the issue is on rdcycle - there is a discussion of this on the PULP forum here: https://pulp-platform.org/community/showthread.php?tid=133

Based on the above post, I think that essentially coremark assumes it's running in some kind of user mode environment with the ability to use `rdcycle`. Ariane doesn't seem to...

Since this caught my attention and I've seen others complain of the same problem, I decided to help out the Ariane project and implement the registers (option 2). You can...

You can set -rtl_timeout to a large number. I think it's in either micro or nanoseconds. In other circumstances I've set it to something around 1000000 to stave off the...