Jonathan Balkind

If you're following these excellent instructions as I was: https://stffrdhrn.github.io/hardware/embedded/openrisc/2019/06/11/or1k_marocchino.html Then in my case I was able to clone the elf-loader core directly from here: https://github.com/fusesoc/elf-loader Then `fusesoc library add...

Might be worth having some constraint on the names of flags in CAPI to avoid this? I can't remember whether this was purely CAPI1 specific, though.

What if DPI compilation was a generator core in the standard library?

Take a look at the .v.pyv files which produce cache RAMs and see the parameters that are being used in those. Try searching the repo on github for `MakeGenericCacheDefine` to...

Hi Raghav, At present the number of interrupts is hardwired in our scripts. For simulation you can change this line for sources: https://github.com/PrincetonUniversity/openpiton/blob/openpiton-dev/piton/tools/src/sims/sims%2C2.0#L1262 And for FPGA you can change sources...

What does the log that it tells you to check say?

My guess would be that you haven't prebuilt the riscv tests in the ariane subrepo if it can't find dhrystone. Perhaps your running of ariane_build_tools.sh failed and you didn't notice....

Ah then I think you might need to put dhrystone.riscv rather than .c There was also a commit newer than the openpiton branch (on openpiton-dev) which fixed a regression with...

Sanity check: in both cases you put -precompiled rather than --precompiled - which are you using in your command? It should be the latter. I don't see sims printing that...

Wait your commands point to the file you're trying to run (`-f ./piton/design/chip/tile/ariane/tmp/riscv-tests/benchmarks/dhrystone/dhrystone.c`). What you should be doing for pitonstream is creating a file called test.txt (`-f test.txt`) which has...