Ondrej Ille

Results 48 issues of Ondrej Ille

Hi, trying to elaborate some netlists coming from [ORFS](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts), I get errors. If not all ports of a cell are connected, then NVC throws errors. E.g. for a cell like:...

verilog

Hi, It would be useful to have support for "black-box" instances. There would exists a "special list" of entities / modules (passed e.g. via CLI switch or some other config)....

wishlist

Hi, a follow-up for the #1282 issue. The NVC still crashes when the concatenated port is an input, e.g. consider following port: ``` .l2d_r_block_id_r({1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0,...

verilog

Hi, we found a bug in heavily parametrized RTL. Parameters are mixtures of packed and unpacked arrays. This is very reduced example, so don't try to follow the code semantics....

area: elaboration

Hello, verilator errors out when parsing `foreach` after an implication in constraints. A simplified code showing this is: ``` class ahb_transaction; typedef enum logic [2:0] { AHB_SIZE_8, AHB_SIZE_16, AHB_SIZE_32, AHB_SIZE_64,...

area: parser
type: feature-IEEE

Hello, if I try to inherit from a class that by itself is typedef of another class, verilator does not accept this. A minimal example for this is: ``` package...

area: elaboration

Hi, when trying our UVM environment, we run into issues when trying to randomize some of our classes. I stripped down all the UVM stuff from it, so that the...

area: lint
area: randomization