Ondrej Ille
Ondrej Ille
Hi, after seeing [`https://github.com/nickg/nvc/issues/808`](https://github.com/nickg/nvc/issues/808) I gave it a shot at compiling Verilog standard cell libraries I have available for a PDK that we use. I see couple of macros unsupported:...
Hello @RTimothyEdwards, I was wondering whether there is a chance that Magic will ever support Open Access format. I have only very brief knowledge of the politics behind the OA,...
Convert all Cover Items to one Bin per item, make each item counter: 1. [x] Branch coverage - Done only half-way, coverage reporting still uses to mask and flag. 2....
Hi, does PeakRDL-regblock generated register map support clock gating ? I see that each generated register is clock enabled, so inferred clock gating will kick in for individual registers /...
Hi, when trying to synthesize the generated register map with Design compiler, I get warnings due to assertions that check the generated block behavior: ``` Line 1289: Warning: /tmp/dummy_block.sv:83: The...
I am trying to run peakRDL regblok on a block that we are designing. Currently, we are using ORDT, but since the ORDT is not mainteined anymore, we might be...
Hi, I am trying to port my project: https://github.com/Blebowski/CTU-CAN-FD that I run with VUnit from GHDL into NVC. I managed to get everything working, and I can run the regression...
**Describe the bug** Hi, when I run tests on RHEL8, I get crash **To Reproduce** Steps to reproduce the behavior: 1. cd examples 2. ./run_all.sh **Log**: ``` (ts-python-env-yQ9mF3ZL-py3.8) [oille@runner4 examples]$...
The current coverage data format is not usable with other HW tools. To tackle the interoperability, Accelera released UCIS (Unified Coverage Interoperabiliy Standard): https://www.accellera.org/downloads/standards/ucis The aim of this issue is...
I run into trouble analysis PSL assertions that contain sequence implications. E.g.: ``` library ieee; use ieee.std_logic_1164.all; entity psl_sequence_implication is end entity; architecture tb of psl_sequence_implication is signal clk :...