Gate level crash - Port concat input

[Blebowski]

Hi,

a follow-up for the #1282 issue.

The NVC still crashes when the concatenated port is an input, e.g. consider following port:

.l2d_r_block_id_r({1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
        1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, h2l_r_block_id_f_rev_code_w, 1'b0,
        1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1, 1'b0, 1'b0,
        1'b0, 1'b0, 1'b0})

Here most of the input is driven by constant, only part of the input is driven by an actual signal/variable.

I get crash like so:

*** Caught signal 11 (SEGV_MAPERR) [address=(nil), ip=0x436bc7] ***

[0x5446cc] ../src/util.c:906 signal_handler
-->    show_stacktrace();
[0x7f2224ffd98f] (/usr/lib64/libpthread-2.28.so) 
[0x436bc7] ../src/tree.c:598 tree_kind
       assert(t != NULL);
-->    return t->object.kind;
    }
[0x436bc7] ../src/tree.c:28 vlog_is_net
--> static const imask_t has_map[T_LAST_TREE_KIND] = {
       // T_ENTITY
[0x4fc20f] ../src/elab.c:1387 elab_verilog_stmts
-->       if (!vlog_is_net(target)) {
             diag_t *d = diag_new(DIAG_ERROR, vlog_loc(conn));
[0x4fc524] ../src/elab.c:1318 elab_verilog_module
       if (elab_new_errors(&new_ctx) == 0)
-->       elab_verilog_stmts(ei->body, &new_ctx);
[0x4fbfe3] ../src/elab.c:1458 elab_verilog_stmts
-->       elab_verilog_module(NULL, vlog_ident(inst), ei, ctx);
          elab_verilog_ports(inst, ei, ctx);
[0x4fc524] ../src/elab.c:1318 elab_verilog_module
       if (elab_new_errors(&new_ctx) == 0)
-->       elab_verilog_stmts(ei->body, &new_ctx);
[0x4fbfe3] ../src/elab.c:1458 elab_verilog_stmts
-->       elab_verilog_module(NULL, vlog_ident(inst), ei, ctx);
          elab_verilog_ports(inst, ei, ctx);
[0x4fc524] ../src/elab.c:1318 elab_verilog_module
       if (elab_new_errors(&new_ctx) == 0)
-->       elab_verilog_stmts(ei->body, &new_ctx);
[0x455d1e] ../src/rt/model.c:3992 call_with_model
       MODEL_ENTRY(m);
-->    (*cb)(arg);
    }
[0x55223c] ../src/nvc.c:2505 elaborate
       case 'm':
-->       return make_cmd(argc, argv, state);
       case 's':
[0x55223c] ../src/elab.c:2497 process_command
          .modcache  = hash_new(16),
-->       .dotted    = lib_name(work),
          .model     = m,
[0x40db05] ../src/nvc.c:2661 main
-->    const int ret = process_command(argc, argv, &state);

nvc 1.18-devel (1.16.0.r303.g96f426548) (Using LLVM 19.1.7) [x86_64-pc-linux-gnu]

Please report this bug at https://github.com/nickg/nvc/issues

[Blebowski]

Btw. to get an example netlist with FOSS tools, you can e.g. follow a flow from IBEX: IBEX

https://github.com/lowRISC/ibex/blob/master/syn/README.md

It can run with YOSYS + SV2V. Alternatively, you could try yosys-slang, but that is not what the flow in the IBEX repository describes.

You will need a standard cell library (in a .lib format). You can download e.g. the IHP130 std cells at: STD Cells synthesis libraries It should be enough to choose only a single ".lib" file.

Then, the flow will spit you out sth like ibex_top_netlist.v. If you analyze the netlist, and analyze IHP standard cell library behavioral models: Verilog models of STD cells

then you should be able to do sth-like nvc -e ibex_top.

I am not sure it will exhibit the same issues (as mentioned earlier, I have netlist from commercial synthesizer), but it is a good start on simulating verilog netlists.

Btw. the FOSS synthesis flow is a pain. If you can't deal with it, let me know, I will try to help.

[Blebowski]

Hi @nickg ,

I ran some of the flows from: https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts

and scraped standard cells for GF180 and IHP130:

nvc_example.tar.gz

The IHP PNR example can be elaborated. The IHP SYN example sometimes crashes. The GF180 examples fail to elaborate due to "not all pins being connected", I will open separate issue for this.