Ondrej Ille
Ondrej Ille
This is just a note to track couple of code coverage improvements that I am aware of that are not recorded anywhere: 1. [ ] Allow specifying an entity name...
It may be good to show a warning when a signal declared in package is aliased by a localy defined signal (similar to e.g. when for loop iterator aliases another...
It would be handy to see PSL assertion state in waves, it improves debugability of PSL assertions. I would dump each PSL assertion as one record of: 1. PSL assertion...
Hi, I came across yet another PSL issue. If I have locally clocked PSL assertion in never, NVC does not accept it: ``` entity psl18 is end entity; architecture tb...
Currently `next_a` and `next_e` operators are not supported. NVC fails with: ``` ** Fatal: cannot handle PSL kind P_NEXT_A in build_node > ../src/psl_next_a.vhd:55 | 55 | NEXT_0_a : assert always...
A VHDL simulation initializes value of signal to `type'left`. This may sometimes hide bugs on RTL, that later pop-out on GLS. An example is FSM coded with enum type and...
Hi, it would be really great if there was a way on how to display cells as symbols, not simply as rectangles. That-way the visualized circuit would functionally resemble what...
Hi, would it be possible to support RHEL build please ? Lot of commercial EDA tools work on RHEL, therefore companies use it (or CentOS, Rocky). I was trying to...
**Is your feature request related to a problem? Please describe.** I am trying to visualize a PNR netlist written by a commercial PNR toolchain. We have multiple `.lib` files that...