Rachit Nigam

@priyasrikumar recommends reading this about Adam's writeup on Coq's termination checker: http://adam.chlipala.net/cpdt/html/GeneralRec.html

Couple of related issues: 1. Doing a good job with modules (#118) becomes even more important now since the enumerations might be tied to the definition or usage of particular...

A close analogy is [Scala's match types][scala-match] which allow return types to be changed based on the call site argument. Unsurprisingly, they very quickly become useful in defining dependently typed...

We'd probably want to use the [`sv-parser` library][svp] to support parsing of simple Verilog files and generating Filament stubs out of them. In the long-term, we can hopefully implement various...

Clocks and parameters should probably go in the parameter list instead of the event list since, once a circuit is instantiated, it is only allowed to have one clock or...

Oh interesting! I was thinking of synchronization of values between circuits running in different clock domains but you're talking about the very Filament-esque idea of safety of reuse among different...

This came up again in the context of using Filament within larger Verilog designs. Being able to generate a producer side `ready` signal should be easy: * The `ready` signal...

Awesome! One deeper, language-level problem here is that every port in Filament represents a "stream" of data and Filament programs transform the streams in some way. Here, we seem to...

Absolutely! You may even consider trying to implement a multi ported Verilog memory and giving it a filament. I’d be curious to see how it works and if we can...

This alone is not sufficient because a test suite will generally have a bunch of different files being tested. What about generalizing the `expect_dir` stuff to define a template for...