Generate Filament stub from Verilog module

[rachitnigam]

Build a simple tool that parses a Verilog module's signature and generates a Filament stub out of it. Next step would be to add comments to the Verilog module that can be extracted as signatures directly

[rachitnigam]

We'd probably want to use the sv-parser library to support parsing of simple Verilog files and generating Filament stubs out of them. In the long-term, we can hopefully implement various sorts of analyses on top of this to implement timeline types directly in Verilog.