Rachit Nigam

Yeah, I think it better not be something that changes over time. I think "stable" should mean something like: The port retains the *exact* same value till the next invocation...

The jq stage might be a good example for how to do this: https://github.com/cucapra/calyx/blob/master/fud/fud/stages/jq.py#L24 Essentially, you get access to the `config` field in `_define_steps` where you can get the value...

References: - `bugpoint` command in Yosys: http://www.clifford.at/yosys/cmd_bugpoint.html - `bugpoint` in LLVM: https://llvm.org/docs/Bugpoint.html

Simple script I wrote: ```bash #!/usr/bin/env sh set -euf -o pipefail FILE='trmm.futil' DATA='trmm.data' FLAG1='-p validate -p remove-external-memories -p pre-opt -p compile-empty -p compile-control -p post-opt -p lower' FLAG2='-p validate -p...

For a dumber reducer that might delete conditional-related code: in the first run of the script, calculate the number of cycles (using verilator). Any reduced test case will take no...

It just occurred to me that we can actually turn this into a ~creduce~ [csmith tool](https://embed.cs.utah.edu/csmith/) for Verilog—since we can carefully generate programs with particularly funky control flow, maybe we...

This is already tracked in our Projects and isn't currently actionable so closing

The first step to doing this would be to expose a function on groups to return the assignment representing the done condition.

The problem is the implementation of `match_element`: ``` component match_element(in: 32, prefix: 32, length: 5, ml_done: 1) -> (match_line: 1, write_en: 1) { cells { ... } wires { group...

The solution to fix issue is making it invalid for the `done` signal of groups and components to depend on an input signal. Also, out of curiosity, @cgyurgyik is there...