Rachit Nigam

@jiahanxie353 remind me what problem you were running into?

Closing in favor of #2316. @jiahanxie353 once that is merged, can you make similar changes on the CIRCT side and make the rest of the flow work?

@jiahanxie353 this patch is marked as a draft. Is that intentional? It would be better to review it once it is in a state where the design is mostly fixed...

Okay, the reasons for marking it a draft makes sense @jiahanxie353! > In the scf.parallel's semantics, we are certain that we won't be storing to the same memory address by...

You can look at the [Tracebank paper](https://zhouyuan1119.github.io/papers/tracebank-fpga2017.pdf) for details on how to automatically determine good banking factors. I think optimality exists but for large programs, you might have to use...

Thanks for the bug report @Demindiro! Let me know if you'd like to take a crack at fixing this and I help think through what could be causing the problem!

@ekiwi what needs to be done to get this merged?

Thanks @bcarlet! Can you provide an MRE?

> So, if we want to emit these case statements via the Verilog backend, it would be nice to have an IR construct within the compiler to store these transitions...

Welp, you've managed to demonstrate why I think provide arbitrary assignments is good idea. For: ``` fsm my_fsm { ... s_i: { A, B, C } => s_j, ``` There...