Rachit Nigam

> In terms of an actionable way forward, one approach could modify the [compile_invoke pass](https://github.com/calyxir/calyx/blob/ed4ce6e5980dfb61a289354231dd514105248c7e/calyx-opt/src/passes/compile_invoke.rs) to flatten such components that only have a single group in their control block into...

Thanks for starting this! I should mention: the current `@ControlID` (#1366) and `@NodeID` stuff might also benefit from this. @calebmkim might have thoughts since this is used in resource sharing...

> Maybe there's another way that we can ensure a deterministic order of op registration (including from Rhai files) that would allow this kind of control without scoring. The downside...

Is this issue still relevant given that the `fud2` tracker is also tracking the issue? If it is, let's change the name to something that's more specific to the problem...

You can probably rewrite this to used `assign` instead of the `always_comb`: ```verilog assign test = (acc >= {1'b0, right}); assign true_branch = {acc_next, quotient, 1'b1}; assign false_branch = {acc,...

Calyx does not emit always_comb so the only uses are in the standard library.

Your best bet is the tests we already run in the CI. If you're suspicious of particular things failing, you can try to write more tests.

@parthsarkar17 anything stopping this from being merged?

Ah, good catch. We emit always_ff because the condition might be intermittently be true but we only care about assignments having a unique assignment at the clock boundaries. We need...