Readon
Readon
I suppose what you want is a select stream synchronized with the output stream. The current design is only for asynchronized usage, you need to implement that yourself.
> > I suppose what you want is a select stream synchronized with the output stream. > > The current design is only for asynchronized usage, you need to implement...
> > > as normal definition, mux is a combinational concept, which is natrually asynchronized. also, it is different from stream dispatcher. > > > > > > I understand,...
please only commit changes of logic, but not the auto format ones.
> Okay, thanks for the explanation. I added syncSelc und regSel for StreamDemux. Should be ready for review now. Good job. The only thing I concern about is the function...
> Seems good to me. @Readon All good for you ? Or i missed something ? Ok, it's good to me. Thanks.
If this is good enough, may be documented them is a good idea.
> I don't know if Verilator has a force sementic, i would say it hasn't. I kinda would prefer having that feature being suported the emulated way as shown in...
Formal verification: Verilog generated when using synchronous resets is not understood by SymbiYosys
The problem of your code is ``` .withConfig( Config.spinal ) ``` This line use Spinal's elaboration config which is not compatible with the formal config one, delete it would work.
Formal verification: Verilog generated when using synchronous resets is not understood by SymbiYosys
This might be a solution. ``` scala .withConfig( Config.spinal.includeFormal ) ```