Readon

> Hi, > > I think a way to do it would be to define some new SpinalTag, add them to the SpinalHDL netlist, and have a post elaboration tool...

It seems the existing facility is not easy to reduce the Axi4 to AxiLite4, so should we label this as wontfix?

> Maybe rename it to "Add conversions `AXILite4` `AXI4`" and wait for #1002 to be merged? (If there is the Lite->Full conversion in the PR too) No, they follow different...

> Indeed, but the discussion above shows an evolution of the requirements from the issue author from merging them to implementing conversions. But you are right, this is the quick...

Maybe it's time to use docker image instead of setup environment every time. I have created a base image for SpinalHDL can be used by ``` shell docker pull ghcr.io/readon/spinalhdl:master...

I think it's a good idea to have a docker image that can be used in CI. On other hand, it's really easier for new starter who can skip to...

> Verbose mode did not yield anymore information using curl: > > ``` > # curl --insecure https://172.18.0.1:32768 -v > * Trying 172.18.0.1:32768... > * connect to 172.18.0.1 port 32768...

> Okay, I found (`zsh % grep -r "bitVectorWidthMax" **/src`) it is used only in [Phase.scala:1285](https://github.com/SpinalHDL/SpinalHDL/blob/c54eebf3a424199b36fcb6f21d1e75fd50312aec/core/src/main/scala/spinal/core/internals/Phase.scala#L1285). (I see also [Phase.scala:1297](https://github.com/SpinalHDL/SpinalHDL/blob/c54eebf3a424199b36fcb6f21d1e75fd50312aec/core/src/main/scala/spinal/core/internals/Phase.scala#L1297) and I'm wondering why the literal 4096 is used here...

Have you investigated the reset area described [here](https://spinalhdl.github.io/SpinalDoc-RTD/master/SpinalHDL/Structuring/clock_domain.html#resetarea)? I think this can help with the reset related logic.

> The reset area isn't useful for this purpose. The reset area would also add the reset signal to the internal buffer register which is not needed and therefore makes...