Readon

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Reusing precompile module for capturing simulation wave causes failure in Verilator backend

If anyone is interested in this, I am pleased to introduce the [OSPP project](https://summer-ospp.ac.cn/org/prodetail/250dc0412?list=org&navpage=org).

Llama.cpp now supports distributed inference across multiple machines.

There is also an auto schedule algorithm that [exo](https://github.com/exo-explore/exo) do to mix CPU, GPU resources together. However, exo is a little bit buggy on intel cpu based machine.

ClockDomain.current made CLOCK CROSSING VIOLATION

in Eg1, you have 3 clock domain, 1. Domain.current, 2. aClock, 3. bClock. you just announce that bClock is synced to aClock's clock, but the default Domain.current is not. ```...

Unify conf file for sbt and mill.

> Realistically.. wouldnt someone that uses the template project want to use either sbt or mill and only rarely both? So this would only complicate things. > > IMHO there...

XSim in spinalhdl fail to simulate IPs like FFT or complex multiplier, but works fine in Vivado

do you have minimum example?

Run test for InterfaceTesterCocotbBoot failed when only use 2.11 scala compilier.

@yportne13 Would you please take a look at it? Or maybe we need to consider removing the support of 2.11 then.

Running doSim more than once causes an error and will hang Verilator simulation indefinitely

Personally, I recommend you do not use the latest version.

file miss

How about remove simWorkspace directory and rerun?