Readon
Readon
Formal verification: Verilog generated when using synchronous resets is not understood by SymbiYosys
> Yes this actually works in SYNC reset mode. > > In ASYNC reset mode we actually need to set the SymbiYosys multiclock mode. > > Here my attempt to...
Formal verification: Verilog generated when using synchronous resets is not understood by SymbiYosys
> Can you help me getting the Spinal basic template to run with assumeResetReleaseSync, and GlobalClock without multiclock mode? > > I'm kinda lost here... Those `assumeResetReleaseSync` and `GlobalClock` are...
Formal verification: Verilog generated when using synchronous resets is not understood by SymbiYosys
you can use them by calling withAsync method of FormalConfig.
Formal verification: Verilog generated when using synchronous resets is not understood by SymbiYosys
About the documentation, the formal verification currently is still not widely used, especially the Cross Clocking one. So I want to wait more test before we documented the usage. Because...
Formal verification: Verilog generated when using synchronous resets is not understood by SymbiYosys
@janschiefer Has this issue been solved? If not, how about the #1435 ?
So the dependency graph becomes complex though.
> I have a few concerns. You should keep the refactoring to as little changes as necessary. I understand package names and some imports will change. I also feel we...
When would this be finished?^^ The existing test is really take too much time to finish.
> @Readon thanks for the ping, it is nice to know that what I've been working on will be useful 😃 > > I think I won't be able to...
I think this have been done, so can we close this? @numero-744