Readon

> It isn't fully completted, but better to do it from upstream i think What is still missing currently？

> > What is still missing currently？ > > https://github.com/SpinalHDL/SpinalHDL/tree/dev/tester/src/test/scala/spinal/tester/scalatest is still full of things :) ahh, that is only remained for the balance for running time of ci test.

use translateWith might be better option

The function onWrite is definied as register function whose logic would be activated while "a write transaction occur on address". In many buses that data and address are transferred almost...

fusesoc is convenient to help on generating FPGA project, such as project for Xilinx Vivado. Only source files and fusesoc core file is required to keep in version control tools....

> @chenbo-again sorry for the dumb questions above, I don't know much about FuseSoC so I don't really know how it would handle different options for clock/reset polarity - or...

> @Readon I had understood what fusesoc is. My question was whether the current code is missing options for clock/reset settings - which it seems you'd agree that those should...

> I'm not talking about the signals themselves: As you know in SpinalHDL we can choose clock and reset polarity, as well as whether reset is sync/async. The question it...

> > I'm not talking about the signals themselves: As you know in SpinalHDL we can choose clock and reset polarity, as well as whether reset is sync/async. The question...

you can import spinal-tester as below: ``` scala val spinalTester = "com.github.spinalhdl" %% "spinalhdl-tester" % spinalVersion % "test" libraryDependencies ++= Seq(spinalCore, spinalLib, spinalIdslPlugin, spinalTester) ``` directly use scalatest, especially using...