Julian Kemmerer

Hi there, thanks for reaching out - and an excellent question: Why C? Because in 2014 as an FPGA engineer I was in a world where, software folks, who know...

PipelineC++ :eyes: https://github.com/JulianKemmerer/PipelineC/discussions/32

Very much related to #65

As seen in the linked discussion, there are routes to faster timing feedback than running full syn+pnr tools - thanks @bartokon. This likely involves estimation/modeling of some sort. Currently `pyrtl`...

https://www.rapidwright.io/docs/Introduction.html#what-is-rapidwright RapidWright may also be an option for Xilinx FPGAs

Wow how interesting that the nextpnr version came back so ...unpredictable... Doesnt seem like results from nextpnr ive gotten before...

@bartokon I want to have distinct issues for the two parts of the fmax finding problem. See #48 for more discussion like this. Can you share your above plots again...

Add preprocess 'pp' command line arg like so? `--pp "-DMYMACRO"` ?

Currently the only "always supplied" preprocessor arg is `__PIPELINEC__`. It feels like supporting a tool known `__SIMULATION__` might be needed to signal parts of PipelineC code that should or shouldnt...

ASYNC_WIRE pragma https://github.com/JulianKemmerer/PipelineC/wiki/Pragmas exists for global wires but only is actually async if separate clock domains - if same clock domain then doesnt actually mark path as async/false...