Julian Kemmerer

OK as discussed there will now be cached files of period values for pipelined built in functions https://github.com/JulianKemmerer/PipelineC/issues/145 - should allow some kinds of better models and predictions for faster...

#48 issue also very much will be interested in that data as it builds up

@suarezvictor the first data points for the pipeline period cache have been uploaded https://github.com/JulianKemmerer/PipelineC/tree/master/pipeline_min_period_cache/vivado/xc7a100tcsg324-1/syn That cache is what results from building the full RT 1080p targetting 148MHz... so in theory...

It will increase in reliability over time as more data points are used to update the cache.(It likely isn't very accurate to start) Or if more specific tests are intentionally...

`register a 0.5 factor, does it mean you made a 2 stage pipeline of 11 bit each` yes `If you used 11 bit, we'll need that number. ` You can...

`how to round up if the operands doesn't have same size?` Round up to the maximum size of the two operands, u32+u16 you would do 32 * pipeline divisor fraction...

Also @suarezvictor I encourage you, if you want good data for a specific operator, write a little demo function of just that operator and do a ex. `--coarse --sweep --start...

Can try to follow up on this work here https://github.com/JulianKemmerer/PipelineC/blob/master/src/DEVICE_MODELS.py

Please see #46 for recent new caching stuff of period values for pipelined built in functions ex. `pipeline_min_period_cache/vivado/xc7a100tcsg324-1/syn/BIN_OP_PLUS_float_8_14_t_float_8_14_t_0.25.delay`

Who knows maybe https://github.com/JulianKemmerer/PipelineC/blob/master/src/DEVICE_MODELS.py will get to this some day?