Julian Kemmerer

Per #68 there is a `#pragma ASYNC_WIRE my_wire` that exists now to mark global wires as async. A similar thing could be applied to local variable + input args as...

Apparently putting output registers on the RAM can make Vivado adding pipelining in the RAM, helping for large RAMs...maybe URAM only? ...neat...

Could use these names names to easily extend some future 'global_bus' concept

Writes to _shared_ globals are going to default behave like WIREs soon per https://github.com/JulianKemmerer/PipelineC/issues/73 Did rename the clk cross bus the global bus - which can carry signals that clock...

Yeah I think suggesting something like some basic FPGA arch modeling as part of pyrtl - to accompany their asic modeling - makes alot of sense (like you said pick...

`Ultra fine tuning` yes I like that phrase In context there is the lowest level of feedback (which pyrtl recently newly can provide) which is `what is the critical path...

Or well I suppose for LUT level you dont _need_ to know what part of the HDL it maps from if you know the delays across LUTs, etc - are...

I think if we took every PipelineC 'raw VHDL' pipelineable primitive, for ex. simple add operator (can divide up an N bit add into however many stages you want*). What...

Remembered this issue why not call it the -O3 flag and say 'now your rendered HDL is unreadable/a netlist of LUTs'? So the PipelineC HDL gets synthesized to LUTs first...

Wow - who would have thought there was so much to be said about optimizing binary to decimal, neat :nerd_face: