Julian Kemmerer

Say you have a `my_pipeline` that is reported to have a `total delay of 100ns`, thats comb. logic without pipeline registers, etc Say your device fmax is 500MHz(`2ns period`). And...

Then it gets feedback from the syn+pnr tool saying. Your `slicing of 50 stages actually got to ~ 350MHz`. What do we do next? It roughly (some hand crafted stuff...

And its that kind of iterative looping - finding out you were off, and trying to re-adjust that exists. `Important:` this method, and anything to immediately replace it works just...

Yeah thats good thinking - perhaps what actually occurs for larger non-`--coarse` designs. In that mode, ex. for our `2ns period` target the tool does a slighty different sweep: it...

Definitely down to have some fun ML experiments to see what better predictions can be done :D

Oh gosh v2 :hourglass_flowing_sand: `We model a circuit as a graph in which the vertex set V is a collection of combinational logic elements and the edge set E is...

This could be literally implemented with VHDL generics somehow but it doesn't need to be an exact copy of the functionality

Hey there @bartokon - something like you suggest is exactly what I want - but is not quite clear how to get there yet. Maybe its faking it by sending...

pragmas for ports with sub-MAIN funcs. for two-func clock crossing 'instance of a file-module' - how to do clk crossing instances? macros?

Static funcs? `Unlike global functions in C, access to static functions is restricted to the file where they are declared`