Julian Kemmerer

Should really produce `vhdl` directory that contains all VHDL files for that final run. Then existing output `.tcl` and `.qip` files pointing into that adjacent vhdl directory should be easy...

Vitis could use AXIS specific mapping of ports ```map_clock clk_300p0_0 map_axi_stream io_and_ctrl_in_data_0 io_and_ctrl_in_valid_0 in_ready_return_output_0 clk_300p0_0 input_stream slave map_axi_stream out_data_return_output_0 out_valid_return_output_0 io_and_ctrl_out_ready_0 clk_300p0_0 output_stream master ``` Some kind of pragma to...

As of closing https://github.com/JulianKemmerer/PipelineC/issues/65 The constant value of the expression is not resolved. But it is known that things downstream/derived from it are constant too (not part of pipeline registers,etc)...

As of https://github.com/JulianKemmerer/PipelineC/commit/ccd0e812bfa728ae8944ad5e2efda61ede34709d the original goal of `never generate registers for the pipeline (just wires)` was completed. As seen in the many comments - this did spawn several related issues...

See https://github.com/JulianKemmerer/PipelineC/blob/master/src/DEVICE_MODELS.py

Lets continue here @suarezvictor You ask: ```how to continue with this outstanding results? Testing it with a larger project like the raytracer? Implementing a model of simple arithmetic/logical operations but...

I think getting to 1) models of basic pipelined operations and then 2) models of 'full netlist' timing are generally what we want. The goal being instead of asking a...

Lets consider the basics first: You can say "pipeline an operation to N stages". Ex. pipeline an 32b adder to 2 stages (16b per stage) And these are the kinds...

> you provide the data, and I try to develop the models. The data is available in the repo path_delay_cache for a few different FPGA parts. Any more data needs...

Yeah I will help create a cache of pipelined operators that can be used to do ``` (operation, operand widths, num stages) -> fmax But num stages has to be...