Greg Chadwick

Thanks for the report. I suspect it's something to do with the Verilator/OpenOCD interface given it works fine on FPGA. I'll see if 8 hardware breakpoints works on Ibex Super...

Quick update: I've had a look at an Ibex Super System build with 8 trigger points on FPGA and all looks to work fine. So whatever is happening here is...

Also some documentation going over the flow internals would be great, though not an immediate priority. Please create an issue to track the need for it (let's make it a...

@ctopal decided to split this into two issues after all, see cosim issue here: https://github.com/lowRISC/ibex/issues/1732 I've left that unassigned for now. Potentially it's something I can look at as I'm...

I have a set of commits on top of Canberk's work in https://github.com/lowRISC/ibex/pull/1811 but no PR yet. Once that is merged this will be complete.

Completed by https://github.com/lowRISC/ibex/pull/1907

Added an estimate to this. The cosim side of things is handled by https://github.com/lowRISC/ibex/pull/1808 what remains is - Produce a double fault in some test (either a new dedicated one...

@GregAC to provide more detailed guidance on checking here

Reassigning to @GregAC I should be able to address this rapidly freeing @hcallahan-lowrisc for other tasks

PR https://github.com/lowRISC/ibex/pull/1916/files to add the double fault checker