Greg Chadwick

Those interested in this topic may wish to look at what we've done on Ibex (https://github.com/lowRISC/ibex). We run spike in lockstep with our CPU simulation (with support for Verilator, VCS...

Need to determine if this is desired for M2.5

Given comments in https://github.com/lowRISC/opentitan/issues/15378 this isn't needed for M2.5

Total effort upped to 1.5 days. PR has been done https://github.com/lowRISC/opentitan/pull/21632 though still needs review and need to check if there's anything to adjust in DIFs/top-level tests.

PR here to switch `tx_empty` to a status type: https://github.com/lowRISC/opentitan/pull/21844 @jesultra @jettr it turns out the existing `tx_empty` was actually the "transmission complete" interrupt you describe it triggers when the...

> Wouldn't either implementation of tx_empty as 1) a true status interrupt on fifo state or 2) an event based interrupt on fifo state and and tx idle cause the...

PR for the above change is here: https://github.com/lowRISC/opentitan/pull/23409

Latest push addresses CI failures, will address the splitting out/merging with other work of the CIP changes separately. This PR should not be merged until the CIP change work is...

I've spun out the first commit, which is a CIP fix that is useful for status interrupt in general to another PR: https://github.com/lowRISC/opentitan/pull/21804 As there's some CI issues with the...

@timothytrippel could you check out the OTTF change? (Final commit)