Greg Chadwick

I have an RTL fix for the issue here: https://github.com/lowRISC/opentitan/pull/23178

Thank you for the report @KatCe I think this boils down to an issue which occurs when Ibex is configured with the writeback stage (`WritebackStage == 1`) but without the...

@alees24 (a new starter at lowRISC) is taking a look at USB device TLT, I've put him in planned assignee for now as he's ramping up currently rather than actively...

Estimate range: 4 - 8

Enabling the icache requires a specific bit to be set by software in the `CPUCTRLSTS` CSR. We have a function that can enable/disable it: https://github.com/lowRISC/ibex/blob/84232a5bfa8b020cd05718b2ae21d8584c942df8/examples/sw/simple_system/common/simple_system_common.h#L99-L114 Also note that in simple...

Unfortunately I cannot attach html files to a github issue so it's just the regression logs available.

Some more signatures investigated whilst looking at other regressions. I won't give details of precise commits/regressions etc as this is just useful information for later triages rather than a particular...

``` riscv_assorted_traps_interrupts_debug_test.10320 ------------------------------------------------ binary: test.bin rtl_log: rtl_sim.log rtl_trace: trace_core_00000000.log iss_cosim_trace: spike_cosim_trace_core_00000000.log [FAILED]: error seen in 'rtl_sim.log' ---------------*LOG-EXTRACT*---------------- 686: 8581206: Illegal instruction (hart 0) at PC 0x952ade74: 0x00010413 687: 8608426: Illegal...

So to confirm you're trying to run a gate-level simulation of Ibex within the simple system environment using Verilator? The line referred to in the error: https://github.com/lowRISC/ibex/blob/3937e484da24a09ae97820b2defe9a85fd7cea4e/examples/simple_system/rtl/ibex_simple_system.sv#L35 Is just the...

Thanks for finding this @mndstrmr I'll be putting a fix together shortly. In the scenario you describe any instruction that's in the IF stage when the clear is executed has...