Greg Chadwick

PR here to improve CSR usage: https://github.com/lowRISC/ibex/pull/1776 Still a couple of holes, may spin them out as separate issues. Will analyze tomorrow and update estimates as needed,

PR now merged, waiver here for the missed coverage: https://github.com/lowRISC/ibex/issues/1795

https://github.com/lowRISC/ibex/pull/1808 implements the basis of this, namely random writes to the `CPUCTRLSTS` CSR along with the cosim changes needed to allow this to pass regressions. That PR only enables `CPUCTRLSTS`...

https://github.com/lowRISC/ibex/pull/1882/files fixes up the CPUCTRLSTS writes so they occur in `riscv_rand_instr_test`. This enables and disables data independent timing during that test.

Probing for faults at the icache -> if stage interface has been added to the co-simulation system. I will leave this issue open to track the need for RISC-DV changes...

PR here: https://github.com/lowRISC/ibex/pull/1334 disables use of MISA in the CSR test which will allow the test to run on more configurations until a better solution is produced.

Sadly this does need a RISC-V DV change. The issue is even with @rswarbrick's suggested change the top two bits have an invalid value, namely `2'b01`. We cannot express a...

See the RISC-V DV PR here: https://github.com/google/riscv-dv/pull/881 This enables us to flexibly specify WARL fields by using a python fragment in the CSR YAML that specifies how values get legalized....

This is completed by #1779 which is undergoing review

Thanks for the report @cnan123, we've got a few of these kinds of issues where in some cases we sit waiting for something to happen that's already happened so wait...