Greg Chadwick

Timeout increased here: https://github.com/lowRISC/ibex/pull/1771 Closing this now as specific timeout causes are being tracked seperately

I am looking at it as part of the work I'm doing around timing/feedthroughs. Two main things to look at: 1. Add better error handling to the bits of python...

Thank you for the detailed report @cappold. We haven't actually yet tested using the random instruction insertion along with the branch predictor so it's not a big surprise there are...

Closing as it's no longer relevant. Tests don't produce this as frequently as they did. Other issues around double fault detection track remaining work.

Thanks for the report @cnan123. Ultimately this is a similar style of issue to https://github.com/lowRISC/ibex/issues/1499 and the resolution is the same. Our co-simulation work will remove the problem.

Shifting this out of the V2 milestone

Determine what, if any, CSR accesses are occurring in random instruction test, we would expect all of these accesses to get stimulated

Begun investigating this. I've worked out how CSR instruction generation is controlled within RISC-V DV. Some extra constraints and work is needed in particular to be able to choose between...

PR here for CSR work on the RISC-V DV side: https://github.com/google/riscv-dv/pull/887 Estimation (along with existing remaining) has been increased. There's some spike work here to sort out co-sim mismatches when...

RISC-V DV PR is good to merge. Ibex and Spike fixes for CSRs have been made. Still need to make a PR to vendor in updated RISC-V DV and set...